The present invention relates generally to non-volatile memories and in particular the present invention relates to the reduction of current leakage through a tunnel oxide layer of a memory cell.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
To program a memory cell, a high positive voltage Vg is applied to the control gate of the cell. In addition, a moderate positive voltage is applied to a drain (Vd) and a source voltage (Vs) and substrate voltage (Vsub) are at ground level. These conditions result in the inducement of hot electron injection in a channel region near a drain region of the memory cell. These high-energy electrons travel through the thin gate oxide (tunnel oxide) towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell that has not been programmed.
A major concern with memory cells is data retention. That is, how long a programmed cell will retain its programmed state. Electrons placed on the floating gate of a cell by hot electron injection will eventually traverse back across the tunnel oxide over a period of time. When electrons traverse the tunnel oxide during a storage cycle or idle period (a period of time where no other operation is being performed on a programmed cell), the cell is said to have a xe2x80x9cleakage current.xe2x80x9d This leakage current will eventually cause a total discharge of the cell resulting in the loss of programmed data. Thus, it is generally desired to reduce the leakage current during the storage cycle.
The quality of tunnel oxide and the thickness of the tunnel oxide layer determine the rate of leakage current through a tunnel oxide. Generally the thinner the layer of tunnel oxide, the faster the flow of leakage current. Moreover, the reduction in thickness of the layer of tunnel oxide also causes the quality of the tunnel oxide to be degraded thereby increasing the flow of leakage current. In addition, the quality of the tunnel oxide will degrade over time as it becomes subjected to more and more programming and erase operations. A typical thickness of a tunnel oxide layer is around 60 xc3x85. At this thickness, 5 to 9 volts is needed to induce the hot electron injection.
Memory systems that require less energy consumption are desired in the industry. Therefore, a cell with a thinner layer of tunnel oxide is desired since a thinner tunnel oxide layer allows for lower operational voltages to be used in programming the cell. That is, the thinner the tunnel oxide layer, the less voltage is needed to induce hot electron injection.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a Flash memory device having memory cells with a thin tunnel oxide layer that reduces leakage current.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
A method of operating a non-volatile memory cell is disclosed that comprises, placing electrons on a floating gate of the memory cell and then placing positive charge on a control gate of the memory cell to improve data retention. The positive charge causes the electrons on the floating gate to migrate away from a tunnel oxide layer of the memory cell.
Another method of operating a non-volatile memory cell comprises, storing electrons on a floating gate of the memory cell and then supplying a positive voltage on a control gate of the memory cell. The positive voltage attracts the electrons on the floating gate away from a tunnel insulation layer of the memory cell.
A method of operating a memory system comprises, placing non-volatile memory cells in a programmed state, storing positive charge on a control gate of each programmed memory cell to improve data retention, wherein the positive charge causes electrons on a floating gate of each of the programmed memory cells to migrate away from a tunnel oxide layer of each of the programmed memory cells, and powering down the memory system.
A method of operating a non-volatile memory system having blocks of memory cells comprises, storing data in program registers associated with blocks having programmed memory cells and then placing positive charge on control gates of memory cells in blocks having programmed memory cells based on the data stored in the program registers. The positive charge attracts electrons on floating gates of the memory cells away from tunnel oxide layers of the memory cells thereby improving data retention of programmed memory cells.
In one embodiment, a Flash memory device includes a memory array of multiple memory cells and control circuitry. Each memory cell comprises a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate. The control circuitry is used to control memory operations and couple a positive charge to the control gate of the memory cell to attract electrons on the floating gate of the memory cell away from the tunnel oxide layer of the memory cell.
In another embodiment, a non-volatile memory device includes a memory array of multiple memory cells, a power supply and a state machine. Each memory cell comprises a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate. The state machine is used to control memory operations. Once a memory cell is programmed the state machine directs the power supply to apply a positive voltage to the control gates of the memory cell to attract electrons on the floating gate of the memory cell away from the tunnel oxide layer.
In another embodiment, a non-volatile memory device comprises a memory array having blocks of memory cells, a register for each block of memory cells, a power supply and control circuitry. Each memory cell comprises, a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate. The registers are used to store data that indicates when the block contains a programmed memory cell. The control circuitry is used to couple the power supply to control gates of memory cells in blocks having a programmed memory cell in response to the associated register.
In another embodiment, a non-volatile memory device comprises an array of non-volatile memory cells, a plurality of program registers, a power supply and control circuitry. The array of non-volatile memory cells is arranged in erasable blocks, where each erasable block comprises a plurality of sub-blocks. Each program register is associated with one of the sub-blocks. Moreover, each of the program registers is configured to store a data bit when its associated sub-block contains a programmed memory cell. The control circuitry couples a positive voltage from the power supply to control gates of memory cells in sub-blocks in response to the program register.
In another embodiment, a memory device includes a memory array of non-volatile memory cells and control circuitry. Each memory cell comprises a substrate, the substrate having a channel region, a source, a drain, the channel region of the substrate is positioned between the source and the drain, a tunnel oxide layer having a thickness of approximately 30 xc3x85, a first side of the tunnel oxide is positioned adjacent the source, the channel region of the substrate and the drain, a floating gate, the floating gate having a first side positioned adjacent a second side of the tunnel oxide, the floating gate is further position proximate the channel region of the substrate, a portion of the source and a portion of the drain, a control gate, and a inter-gate dielectric layer, the inter-gate dielectric layer is positioned between the control gate and a second side of the floating gate. The control circuitry is used to store a positive charge on the control gates of the memory cells to attract electrons on the floating gate of the memory cell away from the tunnel oxide layer of the memory cell.
In another embodiment, a Flash memory system includes an external processor to provide commands, a memory array of non-volatile memory cells, a power supply and control circuitry. Each memory cell comprises, a control gate, a floating gate, an inter-gate dielectric layer positioned between the control gate and the floating gate, a substrate, and a tunnel oxide layer positioned between the floating gate and the substrate. The control circuitry is used to receive commands from the processor and to control memory operations. Moreover, the control circuitry directs the power supply to place a positive charge on the control gates of programmed memory cells.